1. Field of the Invention
This invention relates to a memory circuit which requires periodic refresh operations, such as dynamic random access memory, and further relates to a memory circuit in which refresh operations are executed automatically without requiring a refresh command from outside, and which is capable of high-speed internal execution of operating commands from outside. This invention also relates to an integrated circuit device, which, in addition to external commands, is able to automatically generate and execute commands internally.
2. Description of the Related Art
Dynamic random access memory (DRAM) is widely used as large capacity memory. Because DRAM is volatile memory, refresh operations are necessary.
FIG. 1 is a configurational view of a conventional memory circuit. The conventional memory circuit has a clock buffer 10 for input of an external clock signal CLK1 and generation of an internal clock signal CLK1 in sync with this; a command decoder 11 for input of commands in sync with the internal clock signal CLK1; an address buffer 12 for input of addresses; and a data input/output buffer 13 for data input and output. In addition, a control circuit 14 controls operations of a memory core 15 in response to commands CMD input by the command decoder 11. Operations of the memory core are also controlled in sync with the internal clock signal CLK1.
Such clock-synchronous DRAM (SDRAM) has, as refresh operations, auto-refresh and self-refresh. Auto-refresh is a refresh operation which is performed periodically between normal read and write operations, and is executed by means of an auto-refresh command supplied from outside. That is, when an auto-refresh command is input from outside, the command decoder 11 generates an auto-refresh command AR1, and in response to AR1 the refresh control circuit 16 generates an internal refresh command REF. By means of this internal refresh command REF, the control circuit 14 controls the refresh operation. A selector 18 selects the address from the refresh address counter 17 and outputs the address to the address latch circuit 19.
On the other hand, self-refresh is a refresh operation in which the memory device itself executes the refresh operation while in the power-down mode state, in response to refresh timing automatically generated by an internal oscillator OSC. In the power-down mode state, no commands (read or write) are supplied from outside, and so the refresh control circuit 16 generates an internal refresh command REF in response to refresh timing generated with arbitrary timing. Thus, the control circuit 5 14 controls the refresh operation.
In this way, commands are supplied from outside while in the normal operating state, and refresh commands are also supplied from outside and refresh operations executed in response. While in the power-down state, no commands are supplied from outside, and so refresh timing is automatically generated internally and refresh operations are executed.
In this way, in conventional memory circuits the memory controller which controls the memory circuit must control the refresh timing during the interval of the normal operating state. That is, the memory controller is equipped with a timer, and must issue auto-refresh commands to the memory circuit each time the refresh timing occurs. Hence, a problem with the memory controller is the complexity of memory circuit control.
In conventional memory circuits, the control circuit 14 executes control in response to read and write commands supplied in sync with the clock signal. Here, if the control circuit 14 is executing the previous internal operation, the next internal operation is executed in response to the newly supplied command, regardless of previous internal operations. Memory circuits have also been proposed in which, if during execution of the previous internal operation a new command is supplied from outside, that command is refused.
In the above latter case, refusal of a command from the memory controller is undesirable, and so memory circuits generally execute internal operations as-is in response to supplied commands, as in the former case. Hence, in the normal operating state, if a refresh command is issued autonomously within the memory circuit and refresh operations are executed, a command supplied during these operations may disturb the refresh operation. And if, as in the latter case, a supplied command is refused, control by the memory controller becomes even more complex.